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E7765 1.3 GHz Quad Pin Electronics Driver
TEST AND MEASUREMENT PRODUCTS
Description
The E7765 four channel, monolithic ATE pin electronics solutions manufactured in a high-performance complementary bipolar process. The E7765 power consumption can be minimized to accommodate the required performance and levels. The E7765 has bias and other inputs that provide a means to adjust performance versus power consumption. The E7765 operates at data rates up to 1.3 GHz/2.6 Gbps. The power supplies to the E7765 are specified over a wide range to accommodate between -2V, +7V and -0.5V, +4.2V output voltage ranges. The E7765 driver is capable of generating 8V swings over a -2 to +7V range. The driver minimum swing is 100 mV. A differential driver mode configures pairs of adjacent drivers on-chip to drive differential signals from a single data input. The driver pairs are DOUT[0]:DOUT[1] and DOUT[2]:DOUT[3]. The on-chip distribution of the driving signal and the close matching of performance on-chip will result in very low skew for differential output to output.
Features
* * * * * * Four Fully Integrated, Three-Statable Drivers Wide Choice of Range, Performance vs. Power Differential Driver Mode Programmable Driver Rise, Fall Times -2V, +7V Driver Voltage Range Small, 80-Pin LQFP Package
Functional Block Diagram
Channel 0 DBIAS DVH DEN DEN* DE DH
RADJ DOUT FADJ
DVL PON DHI DHI* SEL_DHI DHI DHI* PON DVL DH DEN DEN* DVH DBIAS Channel 1 DE SEL
FADJ DOUT RADJ
Applications
* Memory Testers - Companion Chip to E7725 as Drive-Only Channels * Programmable Clock Drivers * Test Instruments
ANODE Channel 2 DBIAS DVH DEN DEN* DE DH
CATHODE
RADJ DOUT FADJ
DVL PON DHI DHI* SEL_DHI DHI DHI* PON DVL DH DEN DEN* DVH DBIAS Channel 3 DE SEL
FADJ DOUT RADJ
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E7765
TEST AND MEASUREMENT PRODUCTS PIN Description
Refers to efer 1, [0:3] Refers to Channels 0, 1, 2 or 3
Pin #
D river
Pin N ame
D escription
56, 57; 44, 45; 4, 5; 16, 17 52, 49, 9, 12 53, 48, 8, 13 70, 31, 71, 30 69, 32, 72, 29 64, 37, 77, 24 65, 36, 76, 25 67, 34, 74, 27 68, 33, 73, 28 66, 35, 75, 26
C ontrol
D OUT[0:3]
D ri ver output. "Flex" di fferenti al i nput di gi tal pi ns whi ch select the dri ver hi gh or low level. "Flex" di fferenti al i nput pi ns whi ch control the dri ver output bei ng acti ve or i n a hi gh i mpedance state. Hi gh i mpedance analog voltage i nputs whi ch determi ne the dri ver hi gh and low levels. Input currents whi ch determi ne the dri ver output si gnal ri se and fall ti mes. Analog current i nput that sets an i nternal bi as current for the dri ver and i ts overall performance by adjusti ng the overall power.
D HI[0:3] D HI*[0:3] D EN[0:3] D EN*[0:3] D VH[0:3] D VL[0:3] RAD J[0:3] FAD J[0:3] D BIAS[0:3]
47, 14
SEL_D HI[0:1]
TTL i nputs that select the D i fferenti al D ri ve mode when a logi cal hi gh. SEL_D HI[0] wi ll enable D OUT[0] and D OUT[1] to di fferenti al mode. SEL_D HI[1] enables D OUT[2] and D OUT[3] to di fferenti al mode. TTL i nput that powers the dri ver ON and OFF. Logi cal 1 wi ll power ON.
60, 41, 1, 20
Pow er Supplies
PON[0:3]
59, 58, 51; 50 43, 42; 2, 3, 10; 11, 18, 19 62, 61, 55; 46, 40, 39; 79, 80, 6; 15, 21, 22 63, 38, 78, 23
M iscellaneous
VC C [0:3]
Posi ti ve power supply to each of the four dri ver channels (Note 1).
VEE[0:3]
Negati ve power supply to each of the four dri ver channels (Note 1).
GND [0:3]
D evi ce ground to each of the four dri ver channels (Note 1).
7, 54
C ATHOD E, ANOD E
Termi nals of the on-chi p thermal di ode stri ng.
Note 1:
All VEEs must be connected, externally, to the same supply. All VCCs must be connected, externally, to the same supply. All GNDs must be connected, externally.
(c) 2006 Semtech Corp. , Rev. 11, 7/18/06
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E7765
TEST AND MEASUREMENT PRODUCTS PIN Description (continued)
80 Lead LQFP Package Pack ackage 14 1.4mm 14 x 14 x 1.4mm
PON[2] VCC[2] VCC[2] DOUT[2] DOUT[2] VEE[2] CATHODE DHI*[2] DHI[2] VCC[2] VCC[3] DHI[3] DHI*[3] SEL_DHI[1] VEE[3] DOUT[3] DOUT[3] VCC[3] VCC[3] PON[3]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
PON[0] VCC[0] VCC[0] DOUT[0] DOUT[0] VEE[0] ANODE DHI*[0] DHI[0] VCC[0] VCC[1] DHI[1] DHI*[1] SEL_DHI[0] VEE[1] DOUT[1] DOUT[1] VCC[1] VCC[1] PON[1]
80 Lead MQFP 14 x 14 x 1.4 mm Top Side
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E7765
TEST AND MEASUREMENT PRODUCTS Circuit Description
Introduction Figure 1 shows a detailed block diagram of the E7765. Each of the four drivers has independent signal control and voltage inputs. In addition, each driver has independent power-down ability as well as adjustability for output rising and falling edge speeds. Refer to Table 1 for a truth table depicting the different modes of operation of an individual channel. Table 2 expands on the independent operations with a description of the differential drive mode operation. Differential pair[0] consists of drive channels 0 and 1 and are controlled by SEL_DHI[0]. Differential pair[1] consists of drive channels 2 and 3 and are controlled by SEL_DHI[1].
Channel 0 Control DHI[0] X X 0 1 DEN[0] X 0 1 1 PON[0] 0 1 1 1 Output Comments DOUT[0] Off HiZ D VL Driver Enabled, Follow DHI D VH Low Power, HiZ State Driver Disabled (HiZ)
DBIAS[2] DVH[2] DEN[2] DEN*[2] DE DH ANODE Channel 2 Channel 0 DBIAS[0] DVH[0] DEN[0] DEN*[0] DE DH
RADJ [0] DOUT [0] FADJ [0]
DVL[0] PON[0] DHI DHI*[0] SEL_DHI[0] DHI[1] DHI*[1] PON[1] DVL[1] DH DEN[1] DEN*[1] DVH[1] DBIAS[1] Channel 1 DE SEL
FADJ [1] DOUT [1] RADJ [1]
CATHOD
RADJ [2] DOUT [2] FADJ [2]
DVL[2] PON[2] DHI[2] DHI*[2] SEL_DHI[1] DHI[3] DHI*[3] PON[3] DVL[3] DH DEN[3] DEN*[3] DVH[3] DBIAS[3] Channel 3 DE SEL
Channels 1, 2 and 3 similar. SEL_DHI[0] and [1] at logical low. Driver Control Truth Table Table 1. Driver Control Truth Table
FADJ [3] DOUT [3] RADJ [3]
E77 Detailed Block Figure 1. E7765 Detailed Block Diagram
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E7765
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
Diff Mode SEL_DHI[0] 0 1 1 1 1 1 1 1 1 1 1 X 0 1 0 0 1 0 1 0 1 X X X 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 Off Off Off HiZ DVL[0] DVH[0] DVL[0] DVH[0] HiZ HiZ DHI[0] Channel 0 Control DEN[0] PON[0] Output DOUT[0] DHI[1] Channel 1 Control DEN[1] PON[1] Output DOUT[1] Comments
SEL_DHI[0]=0, Channel 0 and Channel 1 are independently controlled (see Table 1) X X X X X X X X X X 0 1 1 X 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 HiZ DVH[1] DVL[1] Off DVH[1] DVL[1] HiZ HiZ DVH[1] DVL[1] Differential mode, both channels enabled. Differential mode, DOUT[0] logically follows DHI[0] Differential mode, DOUT[1] logically follows the complement of DHI[0] Differential mode, PON and DEN are independent per channel.
DHI[1] has no effect in differential mode since the Channel 1 output will follow the complemented state of DHI[0]. Diff Mode SEL_DHI[1] 0 1 1 1 1 1 1 1 1 1 1 X 0 1 0 0 1 0 1 0 1 X X X 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 Off Off Off HiZ DVL[2] DVH[2] DVL[2] DVH[2] HiZ HiZ DHI[2] Channel 2 Control DEN[2] PON[2] Output DOUT[2] DHI[3] Channel 3 Control DEN[3] PON[3] Output DOUT[3]
Comments
SEL_DHI[1]=0, Channel 2 and Channel 3 are independently controlled (see Table 1) X X X X X X X X X X 0 1 1 X 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 HiZ DVH[3] DVL[3] Off DVH[3] DVL[3] HiZ HiZ DVH[3] DVL[3] Differential mode, both channels enabled. Differential mode, DOUT[2] logically follows DHI[2] Differential mode, DOUT[3] logically follows the complement of DHI[2] Differential mode, PON and DEN are independent per channel.
DHI[3] has no effect in differential mode since the Channel 3 output will follow the complemented state of DHI[2].
Diff Control Driver Stat Truth Tables tate Table 2. Differential Mode Control - Driver State Truth Tables
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E7765
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
Driver Driver The driver digital control inputs DHI/DHI* and DEN/DEN* are "Flex Inputs" - wide voltage differential inputs capable of receiving ECL, TTL, CMOS, or custom level signals. Single-ended operation is supported by connecting the nondriven, differential input to the appropriate DC threshold level. Differential input drive is recommended for highest performance. Drive Enable The drive enable inputs (DEN / DEN*) control whether the driver is forcing a voltage, or is placed in a high-impedance state. If DEN is more positive than DEN*, the output will force either DVH or DVL. If DEN is more negative than DEN*, the output goes into a high impedance state. The DEN/DEN* inputs are independent per drive channel and remain effective in the differential mode. NOT leav Do NOT leave DEN / DEN* floating. Driver Data When the driver is enabled (Table 1) the drive data inputs (DHI / DHI*) determine whether the driver output is forcing a high or a low. If DHI is more positive than DHI*, the driver will force DVH when the driver is active. If DHI is more negative than DHI*, the driver will force DVL when active. The DHI/DHI* inputs are independent per drive channel, but these input signals for drive channels 1 and 3 are not effective when differential mode is enabled. NOT leav Do NOT leave DHI / DHI* floating. Driver Differential Mode Selection The TTL input SEL_DHI will place a pair of drive channels into a differential drive mode. Channels 0 and 1 are a differential pair that is independent from the channel 2 and 3 differential pair.
BIAS 462
SEL_DHI[0] = 1 is used for outputting a differential signal where DOUT[1] is the inverse of DOUT[0] with the minimum of skew, and both drivers respond to the DHI/DHI*[0] signal. More detail is shown in Table 2. Notice that poweron (PON) and drive enable (DEN) controls are all still in effect for individual drivers. SEL_DHI[1] likewise controls the second pair, channels 2 and 3. Driver Levels DVH and DVL are high input impedance voltage inputs which establish the driver's high and low output levels. Driver Bias The DBIAS pin is an analog current input which establishes an on-chip bias current, from which other currents are generated. This current, to some degree, also establishes the overall power consumption and performance of the drivers. Each driver is given its own DBIAS control to allow for varying performance among the four drivers. Ideally, an adjustable external current source would be used to minimize any part-to-part performance variation within a test system. However, a precision external resistor tied to a large positive voltage is typically acceptable. (See figure below.) The optimal DBIAS current is a function of the RADJ and FADJ settings, and cannot be set independently. The established bias current follows the equation: DBIAS = (VCC - 0.7) / (Rext + 462).
Rext VCC
SEL_DHI[0] 0 1
DH[0] from: DHI/DHI*[0] DHI/DHI*[0]
DH[1] from: DHI/DHI*[1] DHI*/DHI[0]
VEE
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E7765
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
Driver Slew Rate Adjustment The driver rising and falling transition times are independently adjustable. The RADJ and FADJ pins are analog current inputs which establish the driver rise and fall times. Ideally, an adjustable external current source would be used for RADJ and FADJ. However, for applications where the rise and fall times are fixed, precision external resistors to a positive voltage can be used. The currents into RADJ and FADJ follow the equation: RADJ, FADJ = (VCC - 0.7) / (Rext + 550). Thermal Monitor An on-chip thermal diode string of five diodes in series exists (see figure below). This string allows accurate die temperature measurements. An external bias current of 100 A is injected through the string, and the measured voltage corresponds to a specific junction temperature with the following equation: Tj[C] = {(ANODE - CATHODE) / 5 - 0.768} / (-0.00169).
ANODE
Bias Current
Rext RADJ, FADJ 550
Temperature Coefficient = -7.9 mV / C
VCC
Rise/Fall Adjust Current VEE
CATHODE
The diagrams opposite show how driver rise and fall are adjusted by RADJ, FADJ and DBIAS.
Power Supply Sequencing In order to avoid the possibility of latch-up, the following power-up requirements must be satisfied: 1. 2. 3. VEE <= GND <= VCC at all times VEE <= Analog Inputs <= VCC VEE <= Digital Inputs <= input max voltage or VCC, whichever is less
Power Down of the Driver Referring to Table 1, there are configurations in which a driver can be put into a power down mode, and others in which the driver is powered and ready for operation. PON[0:3] are the TTL inputs controlling power to the individual driver circuits. A logical 1 will power up the driver. The PON inputs remain effective on a per-driver basis in differential mode.
The following sequencing can be used as a guideline when powering up the E7765: 1. 2. 3. 4. VEE VCC Digital Inputs Analog Inputs
The recommended power-down sequence is the reverse order of the power-up sequence.
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E7765
TEST AND MEASUREMENT PRODUCTS
Application Information
Computing the Driver Output Voltage Range The output voltage range of the driver at the DOUT pin is defined by two fundamental calculations. First is the relationship to the power supply voltages at the device (VCC and VEE) and second to the range of programmability of the DVH and DVL input voltages. Remaining in the calculated output voltage range is required to maintain all the DC and AC accuracy specifications for the driver function. The DOUT range relative to the power supply voltages is straightforward and depicted in the following figure at the output of the driver. The required DOUT range must comply with the noted headrooms to the VCC and VEE power supplies. Headrooms larger than noted is also acceptable but must remain within the power supply recommended operating ranges.
VCC
specifications require that the DVH/L input programming range be greater than the required DOUT voltage range if the worst case offset and gain figures are used. The equation for the resulting minimum and maximum voltage at DOUT is; VDOUT(MIN/MAX) = VOFFSET(MIN/MAX) + [ VIN * GAIN(MIN) ] Solving for VIN; VIN = [ VDOUT(MIN/MAX) + VOFFSET(MIN/MAX) ] / GAIN(MIN) To solve for the range of VIN, first select the Vout ranges required. For example, if we choose -2.0V for the minimum end and +6.5V for the maximum end of VDOUT, and an offset min/max of -100mV/+100mV and a minimum gain of 0.975 the equations solve as; For -2.0V; VIN(-2V) = [ -2.0V - 100mV ] / 0.975 = -2.154V For +6.5V; VIN(+6.5V) = [ +6.5V + 100mV ] / 0.975 = +6.769V These resulting VIN values then need to meet the headroom requirements previously mentioned as well as the absolute (relative to ground) voltage limitations specified in the DC specifications data. Computing Po Consumption Computing Maximum Power Consumption The diagram below shows the power consumption of the E7765 as a function of power supply and performance bias settings.
3.5V
4.0V
3.8V
D V H
D V L
or
DVH
DOUT
D O U T
DVL
T
4.0V
3.5V
3.7V
Power Dissipation
VEE
Covers Complete Range of Supplies (All PON=1) 11.0 10.0 9.0 Power (W) High Performance 8.0 7.0 6.0 5.0 4.0 Min Supplies Typ Supplies Max Supplies Lower Performance
The DOUT range is also dependant on the allowable programming voltages at the DVH and DVL inputs. Each of these inputs have similar requirements for power supply headrooms as DOUT does. These headrooms are also depicted in the figure. Furthermore, the DVH/L inputs will have voltage offsets and gain error specifications. These
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E7765
TEST AND MEASUREMENT PRODUCTS
Application Information (continued)
The power consumption goes up as the power supplies are raised in voltage, and the RADJ, FADJ and DBIAS settings are increased for higher frequency performance. There are specifications and graphs for the relationships of these controls to overall performance in the DC Specifications section. Refer to them for choosing the settings for a particular system performance. This section deals with how to heatsink the various power dissipation levels. Cooling Considerations Depending on the applied power supply levels and bias conditions the E7765 will use, various methods of heatsinking will be required to keep the maximum die junction termperature within a safe range and below the specified maximum of 100C. the heatsink and at what angle the air is impacting the heatsink. There are many options available in selecting a heatsinking system. The formula below shows how to calculate the required maximum thermal impedance for the entire heatsink system. Once this is known, the designer can evaluate the options that best fit the system design and meet the required R. R(heatsink_system) = (TJmax - Tambient - P * JC) / P where, R (heatsink_system) is the thermal resistance of the entire heatsink system TJmax is the maximum die temperature (100C) Tambient is the maximum ambient air temp expected at the heatsink (C) P is the maximum expected power dissipation of the E7765 (Watts) JC is the thermal impedance of the E7765 junction to case (0.8C/W)
R of Heatsink System ( C/W)
The E7765 package has an integral heat slug located at the top side of the package to efficiently conduct heat away from the die to the package top. The thermal resistance of the package to the top is the JC (junction-to-case) and is The graph below uses the power estimates from the previspecified at 0.8C/Watt. ous graph and indicates the required maximum thermal impedances required for the heatsinking system using the In order to calculate what type of heatsinking should be above formula with Tambient at 35C. applied to the E7765, the designer needs to determine to taken the worst case power dissipation of the device in the appli- Care needs to be taken when increasing the operating cation. The graph above gives a good visual relationship of DBIAS, RADJ, FADJ inputs. Monitoring the die temperaRADJ, FAD inputs. Monitoring ADJ tem emperaery adequat uate airflo flow ver the range of power dissipation that can be expected from ture to insure adequate heatsinking and air flow is ver y to impor portant. the E7765. The range of power covers the different modes impor tant. . of operation, power supply settings, and performance bias adjustments available. Use the data and graphs in subseRequired Heatsinking Thermal Resistances Covers Complete Range of Supplies (All PON=1) quent sections to determine a particular applications power 16.0 dissipation.
14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 Min Supplies Typ Supplies Max Supplies
Another variable that needs to be determined is the maximum ambient air temperature that will be surrounding or blowing on the device and/or the heatsink system in the application (assuming an air cooled system). A heatsinking solution should be chosen to be at or below a certain thermal impedance known as R in units of C/Watt. The heatsinking system is a combination of factors including the actual heatsink chosen and the selection of the interface material between the E7765 and the heatsink itself. This could be thermal grease or thermal epoxy, and they also have their own thermal impedances. The heatsinking solution will also depend on the volume of air passing over
More information on heatsink system selections can be read on heatsink vendors' web sites and in the Semtech Application Note #ATE-A2 Cooling High Power, High Density Pin Electronics.
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E7765
TEST AND MEASUREMENT PRODUCTS
Application Information (continued)
E7765 Hookup
VEE[2]
DVL/DVH, DBIAS, RADJ, FADJ[2] DEN[0,2]
DVL/DVH, DBIAS, RADJ, FADJ[0]
VEE[0]
5
4
5
80,79,6 PON[2] VCC[2] 2,3 DOUT[2] CATHODE DHI[2] 3pF 7 2 8,9 10,11 6 1
78
73-77
69-72
64-68
63
61,62,55 60 VCC[0] 59,58 55 DOUT[0 3pF 54 52,53 50,51 2 ANODE DHI[0] VCC[0,1] PON[0]
CH[2]
CH[0]
VCC[2,3]
DHI[3] SEL_DHI[1] DOUT[3]
2
12,13 14 15
48,49 47
2
DHI[1] SEL_DHI[0] DOUT[1
CH[3]
CH[1]
46 VCC[1] 3pF
3pF VCC[3] 18, 19 PON[3] 20 15,21,22 23 24-28 29-32 33-37 38
43,42 41 46,40,39 PON[1]
5
4
5
VEE[3]
DVL/DVH, DBIAS, DEN[3,1] RADJ, FADJ[3]
DVL/DVH, DBIAS, RADJ, FADJ[1]
VEE[1]
VEEs, VCCs and GNDs of all channels must be connected together. All capacitors shown are 0.1F unless otherwise noted.
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E7765
TEST AND MEASUREMENT PRODUCTS
Package Information
14 1.4 Pack ackage Down) 14 x 14 x 1.4 mm, 80-Pin LQFP Package (Die Down) (with Exposed Metal Heat Slug) Metal
D D1 N EXPOSED HEAT SLUG 1 9.65 .50 DIA.
DIMS. A
-A- -B- E1 E
TOL. MAX 1.60 .05 m in/.15 m ax .05 .20 .05 .20 .05 +.15/-.10 BASIC .05 1.40 16.00 14.00 16.00 14.00 0.60 0.65 0.30 0 - 7 MAX MAX 0.13 0.10
A1 A2 D D1 E
-D-
HEAT SLUG INTRUSION .0127 MAX.
E1 L
View Top View
e b ddd ccc
STANDOFF
A
A1
A2
SEATING PLAN
.25
L
b
ddd M C A-B S DS
-C-
LEAD COMPLANARITY
ccc C
NOTES: 1) All dimensions in mm. 2) Dimensions shown are nominal with tol. as indicated. 3) L/F: EFTEC 64T copper or equivalent, 0.127 mm (.005") or 0.15 mm (.006") THICK. 4) Foot length "L" is measured at gage plane at 0.25 above the seating plane. 5) Lead finish 85/15 Sn/Pb.
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E7765
TEST AND MEASUREMENT PRODUCTS
Absolute Maximum Ratings
Parameter VCC (relative to GND) VEE (relative to GND) Total Power Supply Digital Input Voltages Digital Differential Input Voltages Digital TTL Inputs Input Voltages Current Inputs Analog Input Currents Driver Output Current Driver Swing Storage Temperature Junction Temperature Soldering Temperature (5 seconds, .25" from the pin) Symbol VCC VEE VCC - VEE DHI(*), DEN(*) DHI(*), DEN(*) SEL_DHI, PON DVH, DVL RADJ, FADJ, DBIAS RADJ, FADJ, DBIAS Iout DVH - DVL TS TJ TSOL VEE -2.5 -2.5 VEE -0.5 0 -40 0 -65 Min 0 -6.5 Max 11.75 0 18.25 VCC 2.5 VCC VCC 2.5 2 40 11.5 150 125 260 Units V V V V V V V V mA mA V uC uC uC AM1 AM2 AM3 AM5 AM6 AM7 AM8 AM10 AM12 AM15 AM16 AM18 AM19 AM20
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these, or any other conditions beyond those "recommended", is not implied. Exposure to conditions above those "recommended" for extended periods may affect device reliability.
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E7765
TEST AND MEASUREMENT PRODUCTS
Recommended Operating Conditions
Parameter Positive Power Supply Negative Power Supply (Note 1) Total Analog Supply Analog Inputs Driver Bias Current Driver Slew Rate Adjustments Thermal Resistance of Package (Note 2) Junction Temperature
Symbol VCC VEE VCC - VEE
Min 8 -6.25 12.2
Typ 10 -5 15
Max 11.6 -4.2 17.85
Units V V V
DBIAS RADJ, FADJ
0.6 0.9 0.8
mA mA uC/W 100 uC
TJ
40
Note 1: For `Negative' ECL "Flex" inputs (DHI, DEN) with range down to -2V input voltage, VEE - -4.75V. Note 2: Measured at top of package on exposed heat slug.
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E7765
TEST AND MEASUREMENT PRODUCTS
DC Characteristics (continued)
Parameter Control Inputs (SEL_DHI, PON) Input Low Level Input High Level Input Bias Current Parameter DRIVER Circuit Output Range Analog Inputs High Level Low Level VIL VIH IIN Symbol DOUT DOUT DVH DVH DVL DVL DOUTSW I_in DBIAS RADJ, FADJ VDBIAS, VRADJ, VFADJ Imax Rout 0 2 -50 Min -2.0 VEE + 3.7 VEE + 4.0 -1.5 VEE + 3.5 -2.25 0.1 -35 0.5 0.3 -0.2 -35 4.0 -1 -500 Typ 0.8 5 50 Max +7.0 VCC - 3.8 VCC - 3.5 +7.4 VCC - 4.0 +6.5 8.0 +35 1.5 1.5 +2.0 +35 8.0 +1 +500 V V A Units V V V V V V V A mA mA V mA A nA Symbol Min Typ Max Units
Driver Swing Input Current Driver Bias Slew Rate Adjustments RADJ, FADJ, DBIAS Voltage Compliance Driver Output (Note 1) DC Output Current Output Impedance (@ 25mA) (Note 3) HiZ Leakage (Driver HiZ, Powered Up) HiZ Leakage (Driver HiZ, Powered Down) DC Accuracy (Note 1) {DESIGN_SPEC: Determine Offset + Gain} Offset Voltage (@ DVH = DVL = 0) Offset Tempco (DVL = 0V, DVH = 3V) Gain (Measured @ allowable -FS and +FS) Linearity (Full Range @ 0V and 75% of DVH/L max input calibration points) (Note 4) Digital Inputs (DHI/DHI*, DEN/DEN*) Input Voltage Range (Note 2) Differential Input Swing Input Current Input Capacitance
4.7
DVH, DVL - DOUT DOUT/C DOUT/DVH, DOUT/DVL DOUT INL
-265 0.5 0.965 -10
+265 1.0 +10
mV mV/C V/V mV
DHI(*), DEN(*) |Input - Input*| Iin
Cin
-2.0 0.24 -300
+5.0 2.0 +300 3.0
V V A pF
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E7765
TEST AND MEASUREMENT PRODUCTS
DC Characteristics (continued)
DC conditions (unless otherwise specified): Over the full "Recommended Operating Conditions". Note 1: Note 2: Note 3: Note 4: See Applications Section describing the applicable "DRIVER OUTPUT RANGE" as a function of VCC and VEE. Digital Input Voltage Range also > VEE + 2.75V. The typical value for Rout should be used to calculate the external resistor for matching to the application's transmission line impedance. The 2-point calibration for full range should be done at 0V and 75% of the maximum DVH and DVL input. While the 1st calibration point (0V) will be the same for both DVH and DVL, the 2nd calibration point will be different (ie. DVH: 75% * (VCC - 3.5), DVL: 75% * (VCC - 4.0)).
Parameter Power Supply Currents All Drivers Powered ON (PON = 1) Positive Supply Negative Supply All Drivers Powered Down (PON = 0) Positive Supply Negative Supply
Symbol
Min
Typ
Max
Units
ICC IEE ICC IEE
-490
390 -450 340 -350
430
mA mA mA mA
370
-420
DC conditions: DVL = 0V, DVH = 3V, SEL_DHI[0:1] and DHI[0:3] at logical low. DBIAS = 0.6mA, RADJ = FADJ = 0.9mA.
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TEST AND MEASUREMENT PRODUCTS
DC Characteristics (continued)
Highest Performance Total Power Curves
12 11 10
PON = 1
Power (W)
9 8
PON = 0
7 6 5
Minimum Typical Power Supply Settings Maximum
Lower Performance Total Power Curves
8 7
Power (W)
PON=1
6 5 4 3 Minimum Typical
Power Supply Settings
PON=0
Maximum
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TEST AND MEASUREMENT PRODUCTS
AC Characteristics
Test Circuit AC Test Circuit
50 Transmission Line (20 inches, ~2 ns) (RL) 953
45.3 DOUT
3pF
Oscilloscope 50
C
C 3 pF 3 pF 5 pF 8 pF
VSWING 0.8V (ECL) 0.3V (LVDS) 3.0V (LVTTL) 5.0V (CMOS/TTL)
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TEST AND MEASUREMENT PRODUCTS
AC Characteristics (continued)
Parameter DRIVER Circuit (DBIAS = 0.6mA) (RADJ = FADJ = 0.9 mA unless otherwise noted) Output Impedance (@ 25mA over temperature and power supplies) Propagation Delay (0 to 1V Output) (Note 1) Data (DHI) to Output (Figure 5) Output Active to HiZ (Figure 4) HiZ to Output Active (Figure 4) Rise/Fall Times (Figure 6) 0 to 1V (20% - 80%) 0 to 3V (10% - 90%) Crossover Voltage Error (Figure 9) Fmax (RL=50, swing=programmed value) (Note 2) (Figure 7) 0 to 1V 0 to 3V Pulse Width (RL=50, swing=programmed value) (Note 2) (Figure 3) 0 to 1V 0 to 3V Pulse Width Dispersion to Minimum Pulse Width (PWmin = 0.5 ns, 50 terminated) (Figure 2) Driver-to-Driver Skew (Diff. Driver Mode) (Note 3) Output Capacitance Delay Tempco (Figure 5) (Switching DVH and DVL) Delay Symmetry (same driver, 1.0V swing) (Figure 5) Trans. Time Matching (same driver) (Figure 6) DOUT = 1.0V DOUT = 3.0V Overshoot/Undershoot (Figure 8) DOUT = 1.0V DOUT = 3.0V Ringback (Figure 8) DOUT = 1.0V DOUT = 3.0V Voltage Crosstalk (when switching adjacent channel) DOUT = 1.0V DOUT = 3.0V Timing Crosstalk DOUT = 1.0V DOUT = 3.0V Tpw Cout Tpd/uC |TPHL - TPLH| Tr,f Tr,f 0 0 10 4.6 1 Symbol Min Typ Max Units
Rout TPLH, TPHL TPAZ TPZA Tr/Tf Tr/Tf VXOVER
4.0 0.5 0.75 1.0
6.0
8.0 1.5 1.5 2.0
ns ns ns ns ns %
0.13 0.55 45
0.25 0.6 55
Fmax Fmax Tpw
1200 600
1300 700
MHz MHz
0.6 0.9 50
30
ns ns ps ps pF ps/uC ps ps ps mV mV mV mV mV mV ps ps
1.5 50 50 100 300 250 250 150
9 12
20 30 12 30
AC test conditions (unless otherwise specified): "Recommended Operating Conditions". VCC = +10V, VEE = -5V. Note 1: Propagation delays for LV_PECL differential logic inputs. Note 2: At 10% output amplitude attenuation. CLOAD in AC test circuit = 0 pF. Note 3: 0 to 800 mV outputs.
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TEST AND MEASUREMENT PRODUCTS
AC Characteristics (continued)
Parameter Control Logic
SEL_DHI (Note 1)
Symbol
Min
Typ
Max
Units
TDIFF_D
50
ns
Note 1:
Includes the time needed to settle new drive levels to within 10% of programmed values.
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E7765
TEST AND MEASUREMENT PRODUCTS
AC Characteristics (continued)
Period = 50 ns Tpw, in1 = 50 ns - PWmin Tpw, in2 = PWmin (DHI - DHI*)
0.0V
Tpw,in1
Tpw,in2
Time
OUT
OUTPUT: OUT(H) = 0.8V; OUT(L) = 0.0V
0.4V
0.0V Tpw,out2 Tpw,out1
Time
Tpw = |(Tpw,in1 - Tpw,out1) - (Tpw,in2 - Tpw,out2)|
The measured result is the absolute value of the change in [Tpw,in - Tpw,out] as the P.W. changes from 25 ns to the end points of PWmin and [50ns - PWmin]. Driver to Dispersion Definition Figure 2. Driver DIN to OUT Dispersion Measurement Definition
Period = 100 ns
OUT Tpw+ VOH VOL + 0.9 * (VOH-VOL) Tpw-
Output Signal
(VOH+VOL)/2
VOL + 0.1 * (VOH-VOL) VOL Time
Driver Definition Figure 3. Driver Minimum Pulse Width Measurement Definition
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E7765
TEST AND MEASUREMENT PRODUCTS
AC Characteristics (continued)
(DEN - DEN*)
0.0V
Time
OUTPUT: DVH = 0.8V, DVL = OUT
TPZA
0.8V
TPAZ
DVH
+800mV 90%
10% 0.0V 10%
Time
DVL
90% 800mV (RLOAD at DOUT = 50 to GND)
Driver Delay Definition Figure 4. Driver HiZ Enable/Disable Delay Measurement Definition
OUTPUT: OUT(H) = 0.8V; OUT(L) = 0.0V (DHI - DHI*)
0.0V
Time
OUT
TPLH +0.8V TPHL
+0.4V
0.0V
Time
Driver to OUT, Symmetr try Trac racking Ske Definition Figure 5. Driver Tpd: DHI to OUT, Symmetr y, and Tracking Skew Measurement Definition
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TEST AND MEASUREMENT PRODUCTS
AC Characteristics (continued)
OUT OUT(H) V1 Tr Tf
V2 0.0V V2 is 0.1 * OUT(H) for 3V and 5V, 0.2* OUT(H) for 0.8V and lower V1 is 0.9 * OUT(H) for 3V and 5V, 0.8* OUT(H) for 0.8V and lower
Driver Transition Transition Matching Definition Figure 6. Driver Transition Times and Transition Time Matching Measurement Definition
Time
OUT
1 / Fmax OUT(H)
0.90 OUT(H)
0.0V
Time
7. Driver Definition Figure 7. Driver Fmax Measurement Definition
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TEST AND MEASUREMENT PRODUCTS
AC Characteristics (continued)
OUT
V2
overshoot
ringback
V1
0.0V
ringback undershoot
Test Cases: V1:V2 = DVL:DVH = DVT:DVH = DVL:DVT
Driver Overshoot, Undershoot, ershoo ndershoo Ringback Figure 8. Driver Overshoot, Undershoot, and Ringback
DVH to DVL XOVER DVL to DVH
800 mV
0V
Driver Crosso ossov Voltage Figure 9. Driver Output Crossover Voltage Measurement
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E7765
TEST AND MEASUREMENT PRODUCTS
Ordering Information
Model Number E 7765A X F EVM7765AXF
P ackag e 14 x 14 x 1.4mm, 80-Pin LQFP with Exposed Heat Slug Edge7765 Evaluation Board
Contact Information
Semtech Corporation Test and Measurement Division 10021 Willow Creek Rd., San Diego, CA 92131 Phone: (858)695-1808 FAX (858)695-2633
(c) 2006 Semtech Corp. , Rev. 11, 7/18/06 24 www.semtech.com

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